A makefile is a special file used to execute a set of actions. The most important purpose is the compilation of programs. Make is a dedicated tool to parse makefiles. Most open-source projects use make to compile a final executable binary, which can then be installed using make install.
In this article, we’ll explore Makefile with basic and advanced examples.
Table of Contents
Makefile Syntax
A Makefile consists of a set of rules. A rule generally looks like this:
targets: prerequisites
command
command
command
- The targets Typically, there is only one per rule. It is not necessary for the target to be a file; it could be just a name for the recipe. We call these “phony targets.”
- The commands are a series of steps typically used to make the target(s). These need to start with a tab character, not spaces. It is also called a recipe.
- The prerequisites are also called dependencies which are separated by spaces.
The target, prerequisites, and recipes together make a rule.
Example of Makefile
Create an empty directory test containing a file Makefile with this content:
test_hello:
echo “Hello World”
In the example above, test_hello behaves like a function name, as in any programming language. This is called the target.
The prerequisites or dependencies follow the target. For the sake of simplicity, we have not defined any prerequisites in this example.
The command echo “Hello World” is called the recipe. The recipe uses prerequisites to make a target. The target, prerequisites, and recipes together make a rule.
Now run the file by typing make inside the directory test. The output will be:
$ make
echo “Hello World”
Hello World
Makefile Example with A Single Target
This makefile has a single target, called new_file. The default target is the first target, so in this case new_file will run.
new_file:
echo “This line will always print”
Makefile Example with Two Commands
This file will make new_file the first time, and the second time notice it’s already made, resulting in make: ‘new_file’ is up to date.
new_file:
echo “This line will only print once”
touch new_file
Makefile Example with Prerequisites
Here, the target new_file “depends” on other_file. When we run make, the default target (new_file, since it’s first) will get called.
It will first look at its list of dependencies, and if any of them are older, it will first run the targets for those dependencies, and then run itself.
The second time this is run, neither target will run because both targets exist.
new_file: other_file
echo “This will run second, because it depends on other_file”
touch new_file
other_file:
echo “This will run first”
touch other_file
Makefile Example with All Targets
We can use all targets to make multiple targets to run. One two three targets will run in the following example.
all: one two three
one:
touch one
two:
touch two
three:
touch three
clean:
rm -f one two three
How to use Makefile in the Make command?
- $ make Make will look for a Makefile called Makefile and will build the default target, the first target in the Makefile.
- To use a Makefile with a different name, use the -f flag e.g. $ make -f build-files/analyze.mk
- To build a specific target, provide it as an argument e.g. $ make isles.dat .If the target is up-to-date, Make will print a message like: make: `isles.dat’ is up to date.
- To see the actions Make will run when building a target, without running the actions, use the –dry-run flag e.g. $ make –dry-run isles.dat Alternatively, use the abbreviation -n. $ make -n isles.dat